FPGA BASED HARDWARE ACCELERATOR DESIGN FOR DEEP CONVOLUTIONAL NEURAL NETWORK - Dwi Cahyo, Ardian
The development of hardware accelerators for deep learning is increasing rapidly with the purpose for flexibility to be applied to various deep learning architectures. Accelerators that are widely marketed today are accelerators with GPU-based architectures where developers encounter quite a lot of disadvantages due to high power consumption. Therefore, further developments for hardware accelerators that can be applied to multiple CNN deep learning architectural models is needed. In this research, the authors will designed an accelerator to be applied to an FPGA. The accelerator will be used to handle processes at the convolution layer of the Convolutional Neural Network (CNN). Processes running on the system are carried out in parallel manners using several processing elements at once. The architecture tested with image data input with resolution of 512×512 pixels that divided into four segments with image resolution of 256×256 pixels. The system designed with target clock base 10 ns and capable to provide throughput of 1Gbyte/sec. Iteration time of the accelerator to process data is 670.980 ns per segment with system latency 7930 ns for 3×3 kernel size. furthermore, Iteration time for the system tested with kernel size of 2×2 is 660,750 ns with latency 7930 ns. The use of accelerators to handle the convolution process in the system is proved to be able to speed up the processing time with a very significant time difference.