DEBLOCKING FILTER DESIGN FOR VIDEO CODEC IMPLEMENTATION USING MPEG4 H.264/AVC STANDARD - SUTANTO (NIM 23205013), ANDREAS
Nowadays, video digital communication is becoming very commonly. In this thesis, it will be designed a filter which is used in MPEG4 H.264/AVC video compression standard, namely Deblocking Filter. In this designed system, filtering process is applied in each decoded macroblock to reduce the block distortion, so a higher picture quality is obtained. This filter functions for block distortion filtering which is appeared from compression process in this standard. For each macroblock, 48 filtering processes are executed, where two blocks data are involved in each process. For each block contains 128 bit data, the total processed data for each filtering are 6,144 data. Because of these large data, a specific design structure is needed so the clock cycle can be minimized. The deblocking filter will be designed using process parallelization of luminance and chrominance filtering process. The memory accesses of this design will also be minimized for getting minimum clock cycles. The functional verification of this design is applied using Synopsys vcs-mx.For hardware verification, the design will be implemented in Altera NiosII Stratix EP1S40F780C5 FPGA development board. After that, the verified design will be synthesized using Synopsys Design Vision and the layout of the design is generated using Synopsys Astro. For the last two processes, the TSMC 0.18u design technology will be used. The design result is compared to the reference design from Huang and Sheng. The design in this thesis needs only 382 clock sequences, smaller than Huang's design (614) or Sheng's design (446). The frame rate of this design (72.1 fps) is also better than Huang's (45.2 fps) or Sheng's (62.3 fps) designs. Number of gates in this design (10.64 K) is also smaller than Huang's (20.66 K) or Sheng's (24 K).