CMOS Low Power Analogue Adder

• Main Author: Tan, Yu Sheng
• Format: Final Year Project / Dissertation / Thesis
• Published: 2020
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utar.edu.my/4045/1/3E_1502289_FYP_report_%2D_YU_SHENG_TAN.pdf; http://eprints.utar.edu.my/4045/
• Institution: Universiti Tunku Abdul Rahman

As the world moves forward into the realm of artificial intelligence (AI), obstacles and challenges keep on popping up along the road. For digital circuit, the main improvement comes in the form of MOSFET downsizing, which will eventually reach a limit. Thus, it is believed that analogue is the way forward to tackle these big challenges. Design of a CMOS low power analogue adder that computes the sum of two analogue inputs voltages is described. In this project, different adder designs are studied and compared. An analogue adder design with low power techniques are proposed which satisfiesthe parameters of power dissipation less than 1mW, time delay less than 10ps and output accuracy greater than 90%. The main focus of the proposed design is on power dissipation and performance. The proposed design utilises the current mode technique as its operational principle, where the inputs voltages are converted to current forms and sum together before converting back to voltage forms. Complementary input pairs and input offset voltage are needed to the proposed design to perform correctly and for the best performance, the inputs voltages must even. In order to reduce the power dissipation, addition MOSFETs are added to the design to limit the current, which reduced the power dissipation by almost 10 times form its original values. The proposed design is constructed and simulated using SAED 90nm process technology in Synopsys custom compiler. The proposed design is able to handle input voltage up to ±1.5V and the output of the design has an accuracy greater than 90%. The accuracy is not able to achieve 100% accuracy due to the current flow accuracy. The layout design of the proposed design is optimized and has a layout area of 22.628µm2 . The power dissipation of the proposed design is dependent on the input voltages, and the maximum recorded power dissipation is 574µW with ±1.5V input voltages. For future work, offset compensation can be implemented to improve the design accuracy and smaller technologies process can improve the overall performance of the design.