Fairness in multiprocessor hardware access to system-on-chip

• Main Authors: Rokon, M. I. R., Motakabber, S. M. A., Alam, A. H. M. Zahirul, Habaebi, Mohamed Hadi, Matin, M. A
• 格式: Conference or Workshop Item
• 語言: English
• 出版: IEEE 2022
• 主題: TK7885 Computer engineering
• 在線閱讀: http://irep.iium.edu.my/100749/1/100749_Fairness%20in%20multiprocessor%20hardware.pdf; http://irep.iium.edu.my/100749/; https://ieeexplore.ieee.org/document/9915675

This paper addresses the acces of multiprocessors into numerous blocks within an SoC (System-on-Chip). The process by which the processor, internal or external, gains the right to access different blocks on an ASIC is first they have issue an access to request a choice-making main block that determines the status of the grant to the processor. In a simple ASIC, a single processor is ideal enough to fulfil all itsd access needs, but dealing with a very complex and large ASIC requires several processors. In this type of case, it is difficult to design and extend the selection block that determines the access of the multi processor to the chip. There are many algorithms to adapt to this initiative. They all have strengths and weaknesses. The purpose of this research paper is to improve strengths and keep weaknesses away. The hardware RTL modelling of the proposed design has been done using Verilog HDL and verified by Verilog test bench. then implemented by the Xilinx Pegasus FPGA device. The Modelsim simulator and Cadence simulator, are both used simultaneously for simulation. The proposed system block can be assembled at any SoC and fabricated from a foundry. Xilinx Pegasus FPGA has been used to implement the hardware in this study and the results show good consistency with expectations and theories.