Multi-sized output cache controllers / Mohd Naqib Johari
This thesis describes the design of a Multi-sized Output Cache Controller that will handle 2Kbyte 16 ways with 4 word block size cache. A cache controller is a device that used to sequences the read and write of the cache storage array [1]. Most of modern microprocessor is designed with multiple cor...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2013
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| Online Access: | https://ir.uitm.edu.my/id/eprint/102748/1/102748.pdf https://ir.uitm.edu.my/id/eprint/102748/ |
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| Institution: | Universiti Teknologi Mara |
| Language: | English |
| Summary: | This thesis describes the design of a Multi-sized Output Cache Controller that will handle 2Kbyte 16 ways with 4 word block size cache. A cache controller is a device that used to sequences the read and write of the cache storage array [1]. Most of modern microprocessor is designed with multiple core architecture that will lead to massive traffic of cache data transfer. By taking the advantage of using temporal locality and spatial locality to the cache, the problem can be solved. With this solution, a controller that capable to handle huge amount of way and block size need to be designed. It also should have the capability overcome the cache coherence. This design will be implemented using Xilinx software. It was developed base on Verilog coding. Using the same software, a test bench was constructed to test the functionality of the controller. This cache controller consists of four stages, from request to read data. It had the capability to read and write to different agent on various output data size from 1byte till 16 byte. |
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