Fast algorithm analysis and bit-serial architecture design for sub-pixel motion estimation in H.264

The sub-pixel motion estimation (SME), together with the interpolation of reference frames, is a computationally extensive part of the H.264 encoder that increases the memory requirement 16-times for each reference frame. Due to the huge computational complexity and memory requirement of the H.264 S...

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Main Authors: Fatemi, M.R.H., Ates, H.F., Salleh, R.
Format: Article
Published: World Scientific Publ CO PTE LTD 2010
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Online Access:http://eprints.um.edu.my/11871/
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Institution: Universiti Malaya
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spelling my.um.eprints.118712017-05-25T08:21:52Z http://eprints.um.edu.my/11871/ Fast algorithm analysis and bit-serial architecture design for sub-pixel motion estimation in H.264 Fatemi, M.R.H. Ates, H.F. Salleh, R. Q Science (General) The sub-pixel motion estimation (SME), together with the interpolation of reference frames, is a computationally extensive part of the H.264 encoder that increases the memory requirement 16-times for each reference frame. Due to the huge computational complexity and memory requirement of the H.264 SME, its hardware architecture design is an important issue especially in high resolution or low power applications. To solve the above difficulties, we propose several optimization techniques in both algorithm and architecture levels. In the algorithm level, we propose a parabolic based algorithm for SME with quarter-pixel accuracy which reduces the computational budget by 94.35% and the memory access requirement by 98.5% in comparison to the standard interpolate and search method. In addition, a fast version of the proposed algorithm is presented that reduces the computational budget 46.28% further while maintaining the video quality. In the architecture level, we propose a novel bit-serial architecture for our algorithm. Due to advantages of the bit-serial architecture, it has a low gate count, high speed operation frequency, low density interconnection, and a reduced number of I/O pins. Also, several optimization techniques including the sum of absolute differences truncation, source sharing exploiting and power saving techniques are applied to the proposed architecture which reduce power consumption and area. Our design can save between 57.71-90.01% of area cost and improves the macroblock (MB) processing speed between 1.7-8.44 times when compared to previous designs. Implementation results show that our design can support real time HD1080 format with 20.3 k gate counts at the operation frequency of 144.9 MHz. World Scientific Publ CO PTE LTD 2010 Article PeerReviewed Fatemi, M.R.H. and Ates, H.F. and Salleh, R. (2010) Fast algorithm analysis and bit-serial architecture design for sub-pixel motion estimation in H.264. Journal of Circuits Systems And Computers, 19 (8). pp. 1665-1687.
institution Universiti Malaya
building UM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaya
content_source UM Research Repository
url_provider http://eprints.um.edu.my/
topic Q Science (General)
spellingShingle Q Science (General)
Fatemi, M.R.H.
Ates, H.F.
Salleh, R.
Fast algorithm analysis and bit-serial architecture design for sub-pixel motion estimation in H.264
description The sub-pixel motion estimation (SME), together with the interpolation of reference frames, is a computationally extensive part of the H.264 encoder that increases the memory requirement 16-times for each reference frame. Due to the huge computational complexity and memory requirement of the H.264 SME, its hardware architecture design is an important issue especially in high resolution or low power applications. To solve the above difficulties, we propose several optimization techniques in both algorithm and architecture levels. In the algorithm level, we propose a parabolic based algorithm for SME with quarter-pixel accuracy which reduces the computational budget by 94.35% and the memory access requirement by 98.5% in comparison to the standard interpolate and search method. In addition, a fast version of the proposed algorithm is presented that reduces the computational budget 46.28% further while maintaining the video quality. In the architecture level, we propose a novel bit-serial architecture for our algorithm. Due to advantages of the bit-serial architecture, it has a low gate count, high speed operation frequency, low density interconnection, and a reduced number of I/O pins. Also, several optimization techniques including the sum of absolute differences truncation, source sharing exploiting and power saving techniques are applied to the proposed architecture which reduce power consumption and area. Our design can save between 57.71-90.01% of area cost and improves the macroblock (MB) processing speed between 1.7-8.44 times when compared to previous designs. Implementation results show that our design can support real time HD1080 format with 20.3 k gate counts at the operation frequency of 144.9 MHz.
format Article
author Fatemi, M.R.H.
Ates, H.F.
Salleh, R.
author_facet Fatemi, M.R.H.
Ates, H.F.
Salleh, R.
author_sort Fatemi, M.R.H.
title Fast algorithm analysis and bit-serial architecture design for sub-pixel motion estimation in H.264
title_short Fast algorithm analysis and bit-serial architecture design for sub-pixel motion estimation in H.264
title_full Fast algorithm analysis and bit-serial architecture design for sub-pixel motion estimation in H.264
title_fullStr Fast algorithm analysis and bit-serial architecture design for sub-pixel motion estimation in H.264
title_full_unstemmed Fast algorithm analysis and bit-serial architecture design for sub-pixel motion estimation in H.264
title_sort fast algorithm analysis and bit-serial architecture design for sub-pixel motion estimation in h.264
publisher World Scientific Publ CO PTE LTD
publishDate 2010
url http://eprints.um.edu.my/11871/
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