Concurrent hardware architecture for dual-mode audio steganography processor-based FPGA
Computer architecture; Field programmable gate arrays (FPGA); Hardware; Parallel processing systems; Programmable logic controllers; Signal to noise ratio; Steganography; Wavelet transforms; Audio steganography; Dual modes; Field programmable logic; Lifting wavelet transforms; Security; Computer har...
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2023
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my.uniten.dspace-230132023-05-29T14:14:11Z Concurrent hardware architecture for dual-mode audio steganography processor-based FPGA Shahadi H.I. Jidin R. Way W.H. 54956597100 6508169028 55936039400 Computer architecture; Field programmable gate arrays (FPGA); Hardware; Parallel processing systems; Programmable logic controllers; Signal to noise ratio; Steganography; Wavelet transforms; Audio steganography; Dual modes; Field programmable logic; Lifting wavelet transforms; Security; Computer hardware description languages Recently, audio steganography has become an important covert communications technology. This technology hides secret data in a cover audio without perceptual modification of the cover audio. Most of the existing audio steganography techniques are unsuitable for real-time communication. Although field programmable logic array (FPGA) technologies offer parallel processing in hardware that can improve the speed of steganographic systems, the research activities in this area are very limited. This paper presents a parallel hardware-architecture for dual-mode audio steganography (DMAS) based FPGA technology. The proposed DMAS reconfigures the same hardware blocks in both hiding and recovery modes to reduce the hardware requirements. It has been successfully implemented on a Xilinx XC6SLX16 FPGA board to occupy only 97 slices. Furthermore, it processes data simultaneously at an operating frequency of up to 58.82 MHz and accomplishes full message retrieval at an embedding rate of 25% with an audio quality above 45 dB in terms of signal to noise ratio. � 2015 Elsevier Ltd . All rights reserved. Final 2023-05-29T06:14:11Z 2023-05-29T06:14:11Z 2016 Article 10.1016/j.compeleceng.2015.03.007 2-s2.0-84925703518 https://www.scopus.com/inward/record.uri?eid=2-s2.0-84925703518&doi=10.1016%2fj.compeleceng.2015.03.007&partnerID=40&md5=26262df9f5e89d8b71cd08c46edf646d https://irepository.uniten.edu.my/handle/123456789/23013 49 95 116 Elsevier Ltd Scopus |
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| description |
Computer architecture; Field programmable gate arrays (FPGA); Hardware; Parallel processing systems; Programmable logic controllers; Signal to noise ratio; Steganography; Wavelet transforms; Audio steganography; Dual modes; Field programmable logic; Lifting wavelet transforms; Security; Computer hardware description languages |
| author2 |
54956597100 |
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54956597100 Shahadi H.I. Jidin R. Way W.H. |
| format |
Article |
| author |
Shahadi H.I. Jidin R. Way W.H. |
| spellingShingle |
Shahadi H.I. Jidin R. Way W.H. Concurrent hardware architecture for dual-mode audio steganography processor-based FPGA |
| author_sort |
Shahadi H.I. |
| title |
Concurrent hardware architecture for dual-mode audio steganography processor-based FPGA |
| title_short |
Concurrent hardware architecture for dual-mode audio steganography processor-based FPGA |
| title_full |
Concurrent hardware architecture for dual-mode audio steganography processor-based FPGA |
| title_fullStr |
Concurrent hardware architecture for dual-mode audio steganography processor-based FPGA |
| title_full_unstemmed |
Concurrent hardware architecture for dual-mode audio steganography processor-based FPGA |
| title_sort |
concurrent hardware architecture for dual-mode audio steganography processor-based fpga |
| publisher |
Elsevier Ltd |
| publishDate |
2023 |
| _version_ |
1806423577086394368 |