An efficient first order sigma delta modulator design
An efficient first order sigma delta modulator has been designed in circuit level, considering the possible non-idealities in 65 nm CMOS technology. This study at first determines the non-idealities of sigma delta modulator. The non-idealities investigated here are clock jitter noise that effects th...
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| Main Authors: | , , |
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2017
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| Online Access: | http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5282 |
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| Institution: | Universiti Tenaga Nasional |
| Summary: | An efficient first order sigma delta modulator has been designed in circuit level, considering the possible non-idealities in 65 nm CMOS technology. This study at first determines the non-idealities of sigma delta modulator. The non-idealities investigated here are clock jitter noise that effects the input signal and increases total error power; then the thermal noise of switches caused by the random fluctuation of carrier that increases the total noise power. Thereafter, circuit leakage causes the limited DC gain and affects signal to noise ratio. Moreover, limited slew rate and gain bandwidth of op-amp, which are both regarded as non-linear gain, reduce signal to noise sum distortion ratio. Based on optimum circuit simulation, the non-idealities are reduced by using folded cascode op-amp at integrator stage with DC gain of 65 dB, slew rate of 3.76 V/μs, and gain bandwidth with 40 MHz. Finally, a first order sigma delta modulator with 8 bit resolution, 64 oversampling ratio as well as power supply of ±2.5 V is successfully designed using PSPICE simulation tool, which can be implemented for practical usage. © 2008 IEEE. |
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