Implementation of convolutional encoder and Viterbi decoder using VHDL

• Main Authors: Wong, Yin Sweet, Ong, Wen Jian, Chong, Jin Hui, Ng, Chee Kyun, Noordin, Nor Kamariah
• Format: Conference or Workshop Item
• Language: English
• Published: IEEE 2009
• Online Access: http://psasir.upm.edu.my/id/eprint/48098/1/Implementation%20of%20convolutional%20encoder%20and%20Viterbi%20decoder%20using%20VHDL.pdf; http://psasir.upm.edu.my/id/eprint/48098/
• Institution: Universiti Putra Malaysia

This work focuses on the realization of convolutional encoder and adaptive Viterbi decoder (AVD) with a constraint length, K of 3 and a code rate (k/n) of 1/2 using field-programmable gate array (FPGA) technology. This paper presents a 4-state, radix-2, hard decision AVD which has the ability to dec...