Investigation Of Cu Interconnect Bulk Resistivity Deterioration As A Function Of Annealing Time

• Main Authors: Abd Rahman, Md Nizam, Muhamad, Razali, Ahmad, Anuar Fadli, Raj, Adrian
• Format: Technical Report
• Language: English
• Published: UTeM 2020
• Online Access: http://eprints.utem.edu.my/id/eprint/25483/1/Investigation%20Of%20Cu%20Interconnet%20Bulk%20Resistivity%20Deterioration%20As%20A%20Function%20Of%20Annealing%20Time.pdf; http://eprints.utem.edu.my/id/eprint/25483/; https://plh.utem.edu.my/cgi-bin/koha/opac-detail.pl?biblionumber=118463
• Institution: Universiti Teknikal Malaysia Melaka

Copper layer metallization is one of the important processes in integrated circuit manufacturing. One of the issues faced in this process is the proneness of Cu interface diffusion as well as surface oxidation which degrade some of the Cu thin film properties. Due to this concern, most integrated circuit manufacturing facility imposed 12 hours maximum delay time between the Cu seed deposition and Cu electroplating step. However, there is lack of study and data to justify support this time restriction. This study investigated the effect of self-annealing time between Cu seeding process and Cu electroplating process to the sheet resistance, reflectance, and stress of the deposited film. The data indicated that the there is no significant deterioration or fluctuation in sheet resistance, reflectance, and stress beyond 12 hours delay time. This suggested that the imposed 12 hours maximum delay time between Cu seed and Cu electroplating process can be further extended, which will give greater flexibility for the manufacturing scheduling