Design and FPGA Implementation of PLL-based Quarter-rate Clock and Data Recovery Circuit

• Main Authors: Alser, Mohammed, Assaad, Maher, Hussin, Fawnizu Azmadi, Bayou, Israel Yohannes
• Format: Conference or Workshop Item
• Published: 2012
• Online Access: http://eprints.utp.edu.my/11988/1/06306128.pdf; http://eprints.utp.edu.my/11988/
• Institution: Universiti Teknologi Petronas

This paper overviews the increased dynamic power consumption issue associated with the use of the serial links as a medium of data communication in today's multi-module based system-on-chip (SoC) and presents a novel all-digital PLL-based quarter-rate clock and data recovery circuit as a potent...