Design and FPGA Implementation of PLL-based Quarter-rate Clock and Data Recovery Circuit

• Main Authors: Alser, Mohammed, Assaad, Maher, Hussin, Fawnizu Azmadi, Bayou, Israel Yohannes
• Format: Conference or Workshop Item
• Published: 2012
• Online Access: http://eprints.utp.edu.my/11988/1/06306128.pdf; http://eprints.utp.edu.my/11988/
• Institution: Universiti Teknologi Petronas

This paper overviews the increased dynamic power consumption issue associated with the use of the serial links as a medium of data communication in today's multi-module based system-on-chip (SoC) and presents a novel all-digital PLL-based quarter-rate clock and data recovery circuit as a potential solution. The proposed architecture works at a frequency equal to one-fourth the received data rate and utilizes a quarter-rate early-late type phase detector, a delay line, a delay line controller, and a digitally controlled oscillator (DCO)-based 8-phases generator. The proposed architecture can be adapted easily for different FPGA families, as well as implemented as an integrated circuit. Moreover, it can be used in a deserializer as part of a SERDES in inter-module communication in SoC. The proposed architecture is designed using the Verilog language and synthesized for the Altera DE2-70 development board. Furthermore, the simulation results validate the expected functionality, such as performing quarter-rate phase detection as well as 1-to-4 demultiplexing. The synthesized design requires 117 logic elements using the above Altera board.