An FPGA-based design and implementation of an all-digital serializer for inter module communication in SoC

In this paper, an all-digital serializer circuit based on a novel frequency and delay locked-loop (F/DLL) clock multiplier is presented. The advantages of the proposed F/DLL are that, it simultaneously generates a high frequency signal from a low frequency reference signal and synchronizes the two s...

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Main Authors:	Assaad, Maher, Alser, Mohammed
Format:	Article
Published:	2011
Subjects:	TK Electrical engineering. Electronics Nuclear engineering
Online Access:	http://eprints.utp.edu.my/7462/1/_pdf http://eprints.utp.edu.my/7462/
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Institution:	Universiti Teknologi Petronas

id	my.utp.eprints.7462
record_format	eprints
spelling	my.utp.eprints.74622017-01-19T08:22:16Z An FPGA-based design and implementation of an all-digital serializer for inter module communication in SoC Assaad, Maher Alser, Mohammed TK Electrical engineering. Electronics Nuclear engineering In this paper, an all-digital serializer circuit based on a novel frequency and delay locked-loop (F/DLL) clock multiplier is presented. The advantages of the proposed F/DLL are that, it simultaneously generates a high frequency signal from a low frequency reference signal and synchronizes the two signals without jitter accumulation issue. Moreover, it can be easily adapted for different FPGA families as well as implemented as an integrated circuit. The proposed serializer circuit is used as a part of a SERDES in inter-module communication in system-on-chip (SoC). The simulation and experimental results confirm the performance of the serializer with the proposed clock multiplier. 2011-11-08 Article PeerReviewed application/pdf http://eprints.utp.edu.my/7462/1/_pdf Assaad, Maher and Alser, Mohammed (2011) An FPGA-based design and implementation of an all-digital serializer for inter module communication in SoC. IEICE Electronics Express . http://eprints.utp.edu.my/7462/
institution	Universiti Teknologi Petronas
building	UTP Resource Centre
collection	Institutional Repository
continent	Asia
country	Malaysia
content_provider	Universiti Teknologi Petronas
content_source	UTP Institutional Repository
url_provider	http://eprints.utp.edu.my/
topic	TK Electrical engineering. Electronics Nuclear engineering
spellingShingle	TK Electrical engineering. Electronics Nuclear engineering Assaad, Maher Alser, Mohammed An FPGA-based design and implementation of an all-digital serializer for inter module communication in SoC
description	In this paper, an all-digital serializer circuit based on a novel frequency and delay locked-loop (F/DLL) clock multiplier is presented. The advantages of the proposed F/DLL are that, it simultaneously generates a high frequency signal from a low frequency reference signal and synchronizes the two signals without jitter accumulation issue. Moreover, it can be easily adapted for different FPGA families as well as implemented as an integrated circuit. The proposed serializer circuit is used as a part of a SERDES in inter-module communication in system-on-chip (SoC). The simulation and experimental results confirm the performance of the serializer with the proposed clock multiplier.
format	Article
author	Assaad, Maher Alser, Mohammed
author_facet	Assaad, Maher Alser, Mohammed
author_sort	Assaad, Maher
title	An FPGA-based design and implementation of an all-digital serializer for inter module communication in SoC
title_short	An FPGA-based design and implementation of an all-digital serializer for inter module communication in SoC
title_full	An FPGA-based design and implementation of an all-digital serializer for inter module communication in SoC
title_fullStr	An FPGA-based design and implementation of an all-digital serializer for inter module communication in SoC
title_full_unstemmed	An FPGA-based design and implementation of an all-digital serializer for inter module communication in SoC
title_sort	fpga-based design and implementation of an all-digital serializer for inter module communication in soc
publishDate	2011
url	http://eprints.utp.edu.my/7462/1/_pdf http://eprints.utp.edu.my/7462/
_version_	1738655579665072128

An FPGA-based design and implementation of an all-digital serializer for inter module communication in SoC

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