Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (D/FLL) Architecture

• Main Authors: Assaad, Maher, Alser, Mohammed
• Format: Citation Index Journal
• Published: 2012
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utp.edu.my/9003/2/546212.pdf; http://eprints.utp.edu.my/9003/
• Institution: Universiti Teknologi Petronas

This paper presents a new architecture for a synchronized frequency multiplier circuit. The proposed architecture is an all-digital dual-loop delay- and frequency-locked loops circuit, which has several advantages, namely, it does not have the jitter accumulation issue that is normally encountered i...