Design of a power-efficient CAM using automated background checking scheme for small match line swing

• Main Authors: Do, Anh Tuan, Yin, Chun, Yeo, Kiat Seng, Kim, Tony Tae-Hyoung
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Conference or Workshop Item
• 語言: English
• 出版: 2013
• 主題: DRNTU::Engineering::Electrical and electronic engineering
• 在線閱讀: https://hdl.handle.net/10356/100930; http://hdl.handle.net/10220/18233
• 機構: Nanyang Technological University

This work reports a fully parallel match-line (ML) structure with an automated background checking (ABC) scheme. MLs are pre-charged by a pulsed current source to minimize power. The proposed ABC scheme monitors the ML sensing using two dummy rows. It digitally adjusts the pulse width and the delay of the search control signals of the CAM without disturbing the normal operation. Therefore, it can continuously track the optimum operating point, making the CAM tolerant to fabrication variations. Additionally, multi-Vt transistors are used in the CAM cell to reduce the leakage by 15× while improving the ML discharge speed by 2× when compared with the standard-Vt devices at 1.2V, 80 oC. The test chip was prototyped using a standard 65 nm CMOS process. The average energy consumption is 0.77 fJ/bit/search at 500 MHz /1.2 V.