A 27–41 GHz frequency doubler with conversion gain of 12 dB and PAE of 16.9%

• Main Authors: Li, Jiankang, Xiong, Yong-Zhong, Goh, Wang Ling, Wu, Wen
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/102734; http://hdl.handle.net/10220/16440
• Institution: Nanyang Technological University

A 27-41 GHz monolithic balanced frequency doubler fabricated using the 0.13 μm SiGe BiCMOS technology is presented in this letter. The balanced doubler consists of a balun, a driver amplifier (DA), a common-base (CB) doubling core and a medium power amplifier. The CB topology is used to increase the bandwidth and for the ease of matching with the balun. The proposed frequency doubler attained a measured gain of 16.8-19.8 dB, an output power of 1.3-4.3 dBm, and a fundamental rejection of better than 25.7 dB (from 27 to 41 GHz) at an input power of 15 5 dBm. An maximum output power of 8 dBm with dc power consumption of 35 mW and corresponding power added efficiency (PAE) of 16.9% have also been achieved. The chip size is 0.75 mm × 0.45 mm.