0.77 fJ/bit/search content addressable memory using small match line swing and automated background checking scheme for variation tolerance

• Main Authors: Do, Anh Tuan, Yin, Chun, Velayudhan, Kavitha, Lee, Zhao Chuan, Yeo, Kiat Seng, Kim, Tony Tae-Hyoung
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Article
• 語言: English
• 出版: 2014
• 主題: DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems
• 在線閱讀: https://hdl.handle.net/10356/105356; http://hdl.handle.net/10220/20473; http://dx.doi.org/10.1109/JSSC.2014.2316241

This work reports a fully parallel match-line (ML) structure with an automated background checking (ABC) scheme. MLs are pre-charged to an intermediate level by a pulsed current source to minimize power. The proposed ABC scheme uses two dummy rows for digitally adjusting the pulse width and the dela...