Design of low voltage low noise folded cascode CMOS op-amp with class AB output stage - Ang, Kok Wai (Nanyang Technological University, 2021)
The market size of IoT devices is expanding rapidly as artificial intelligence and 5G technology are maturing. These smart portable devices require low power performance and a small chip area. The goal of this project is to design a 1.2V supply voltage rail-to-rail input and output operational amplifier with low noise performance. The technology node used in this project is GF 55nm CMOS process. The design in this project is a two-stage op-amp, which comprises a differential folded cascode amplifier with complementary input pair and a feedforward Class-AB output stage. A constant gm bias circuit with start-up circuitry is included in this project to provide the reference current to the op-amp. The challenges of this op-amp design are the undesired variation of input transconductance and the quiescent current of output transistors. The op-amp in this project has achieved a 9% input gm variation over the rail-to-rail common-mode input voltage using hex-pair input structure. The current consumption of op-amp in unity configuration with load (10kOhm and 10pF) is 148.3µA when input common-mode voltage is 0.6V. The input-referred noise voltage of the op-amp is 141.9nV/√Hz at 1 kHz frequency. The design also achieved a 77.9dB open-loop gain with a 77.2° phase margin at the unity-gain bandwidth of 3.10MHz. The open-loop gain is slightly low as the transistors have a large channel modulation index in this process.