Edge processing in IoT using approximate and in-memory computing - Bose, Sumon Kumar (Nanyang Technological University, 2021)
With a large number of sensors getting connected to the internet, scalability of Internet of Things (IoT) has started to hinge on Edge computing-the ability to partly process the raw data at the sensor on the edge of the network instead of transmitting all data to the cloud. However, sensor nodes are typically highly power-constrained due to the limited battery and also requires a long lifetime due to difficulties in replacing nodes in many applications. Hence, this thesis focuses on using different circuit and algorithmic techniques in particular approximate computing, near and in-memory computing (IMC), dynamic voltage and frequency scaling (DVFS) to reduce the energy consumption of edge devices in the Internet of Things. As a first example, we choose predictive maintenance (PdM), one of the most important applications pertaining to IoT in Industry 4.0. Machine learning is used to predict the failure of a machine before the actual event occurs. However, the main challenges in PdM are (a) lack of enough data from failing machines to train binary classifi ers, and (b) paucity of power and bandwidth to transmit sensor data to cloud throughout the lifetime of the machine. In our work, we propose an anomaly detection scheme that can be trained only using healthy machine data. Our Anomaly Detection based Power Saving (ADEPOS) scheme is aimed at saving energy by using approximate computing through the lifetime of the machine. At the beginning of the machine's life, low accuracy computations are used when the probability of the machine being healthy is high. However, on the detection of anomalies, as time progresses, the anomaly detector is switched to higher accuracy modes. Reduction in computation accuracy may be achieved in many ways, such as reducing the number of neurons, reducing the bit width of data, dynamic voltage frequency scaling, etc. Tested on the NASA bearing dataset, ADEPOS demonstrates up to 8.8x reduction of neurons on average over the lifetime of bearings. This resulted in 8.95x energy saving for microprocessor implementation and ~18.8x energy saving in an ASIC implementation, both in 65nm CMOS.