Automatic generation of approximate arithmetic circuits for error- tolerant computing
Approximate computing using approximate circuits are broadly surveyed in the digital design domain. Approximate circuits trade-off accuracy in return for a reduction in design parameters – viz area, total power on-chip and critical path delay. If an application is error-tolerant to a certain degree,...
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| 格式: | Final Year Project |
| 語言: | English |
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Nanyang Technological University
2021
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| 主題: | |
| 在線閱讀: | https://hdl.handle.net/10356/153245 |
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| 總結: | Approximate computing using approximate circuits are broadly surveyed in the digital design domain. Approximate circuits trade-off accuracy in return for a reduction in design parameters – viz area, total power on-chip and critical path delay. If an application is error-tolerant to a certain degree, approximate circuits could be used to speed up the rate of processing. For example, in a digital image processing application, an approximate adder and approximate multiplier could be used to process the image, since minor discrepancies in processed images are imperceptible to human eyes. This report presents the development of a Graphical User Interface (GUI) tool using Python to streamline the Verilog code generation of numerous approximate arithmetic architectures, as well as to compute the error and accuracy of those architectures. |
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