APA引文

Shantanu, R., & Hyoung, K. T. (2022). MRAM integration with L2 memory for a near threshold RISC-V core: Implementing a low power IoT node for AI applications. Nanyang Technological University.

Chicago Style Citation

Shantanu, Raoke, and Kim Tae Hyoung. MRAM Integration With L2 Memory for a Near Threshold RISC-V Core: Implementing a Low Power IoT Node for AI Applications. Nanyang Technological University, 2022.

MLA引文

Shantanu, Raoke, and Kim Tae Hyoung. MRAM Integration With L2 Memory for a Near Threshold RISC-V Core: Implementing a Low Power IoT Node for AI Applications. Nanyang Technological University, 2022.