Hardware implementation of a power efficient CGRA with single-cycle multi-hop datapaths - Su, Lingzhi (Nanyang Technological University, 2022)
Coarse-grained reconfigurable architectures (CGRAs) are computing architectures that provide word-level reconfigurability. CGRAs can achieve high throughput and high power efficiency, while maintaining post-fabrication computing flexibil- ity. In this dissertation, a 167-GOPS/W CGRA design with single-cycle multi- hop datapaths, named PACE, is proposed. The hardware architectures including processing element (PE), algorithm logic unit (ALU), routers, and on-chip pe- ripherals are presented. ALU input gating technique and no operation (NOP) clock gating technique are integrated with PEs to reduce power consumption of the ALU and PE module by 68.66% and 39.11%, respectively.