High-performance CMOS digital multiplier IC design - Chu, Zhuolin (Nanyang Technological University, 2023)
A digital multiplier is a common block in processors, and its speed has a significant impact on the performance of the chip. Many new design ideas have emerged around how to improve the speed of multipliers, including pipeline structure, Wallace Tree structure, and Booth encoding. The Wallace Tree structure increases the speed of partial product summation by compressing the number of partial products; A Carry-look-ahead Adder can be greatly optimized for the addition of multi-bit numbers, and it skips the lengthy bit-by-bit carry propagation process, dramatically increasing the speed of addition operations. Meanwhile, it also reduces the power consumption of the adding circuit by reducing the number of full adders and half adders. Combining the two yields a multiplier with very little circuit propagation delay and power consumption.