Implementation of industry-standard functional coverage in UVM testbench for SoC level verification - Zhang, Shaoyan (Nanyang Technological University, 2023)
As ICs（Integrated Circuits）process technologies and SoC (system-on-chip) design techniques continue to advance, IC chip designs continue to grow in size and complexity. Verification IP automates the generation of test stimulus, data comparison and coverage statistics, and its verification components are well integrated and reused in the SoC system-level verification environment. Therefore, the development of verification IP is of great value to improve the verification efficiency of SoCs and reduce the workload of verifiers. The UVM (Universal Verification Methodology) is a very valuable research tool due to its reusability and ease of use. In addition, the Serial Peripheral Interface (SPI) is the most widely used standard interface protocol in the world, and the APB(Advanced Peripheral Bus)-SPI verification IP is of great practicality. In this thesis, the APB-SPI controller is used as the object of study and its verification IP is built using UVM verification methodology. (1) Completed an in-depth study of the APB-SPI controller module and analyze its functional properties to decompose the functional test points of the design under test. (2) Completed the development of the UVM verification platform for the APB- SPI controller module. Based on the verification plan, the overall architecture of the UVM verification platform was designed and implemented. (3) Completed the functional testing of the APB-SPI controller module and analysis of the test results. After all the test cases were run and passed, regression tests were conducted. Finally, the coverage rate was collected. (4) Completed power estimation for the whole MCU design (including time- based simulation and vector-less simulation) using Ansys Power Artist. The power consumption data of the Arm Cortex-M7 processor AHB bus in the operating state is obtained by time-based simulation. Through vector-less simulation, a series of conditions such as processor frequency, operating temperature, process corner, threshold voltage ratio, etc. are adjusted to obtain the power consumption data of MCU under various limit conditions. This dissertation built a module-level verification environment using the UVM verification methodology based on System Verilog language, and a random test with constraints is implemented, and the simulation is performed using the VCS simulation tool in the linux environment, and the overall code coverage rate reached 97.26% and the functional coverage rate reached 100%, meeting the validation requirements. Besides, through RTL power estimation tool, the power consumption of the entire MCU chip is measured to be 20.188mw(milliwatts), including static power consumption 5.368mw and dynamic power consumption 14.868mw, providing data support for pre-RTL design and post-flow production.