ASIC implementation of a high speed and low power scalar product computation unit - Low, Jeremy Yung Shern. (2009)
This project involves the design, synthesis and placement & routing of improved 16-bit 15-element unsigned inner product architecture. Improvement to the design were made in the carry free addition stage, which is also known as column compression stage or reduction stage, whereby counters are incorporated to perform the preliminary partial product bit accumulation before summation using adders. This report discusses the entire application-specific integrated circuit implementation process, from RTL coding and functional simulations of the proposed architecture to synthesis and timing verification of the design, and finally the placement and routing of the synthesized design.