High-speed CMOS time-domain ADC design - Chen, Qian (Nanyang Technological University, 2023)
Time-domain ADC (TD-ADC) has been emerging recently because of its compact area and energy efficiency for high-speed medium-resolution (8-10 bits) applications. However, the speed superiority of TD-ADC over the voltage-domain comparatives remains to be verified, as the published TD-ADC shows no advantage over SARs in high-speed scenarios. In addition, the voltage scalability of TD-ADC indicated by its digital style has not been reported. To demonstrate the claiming potentials of TD-ADC in conversion speed and technology adaptability, we have conducted comprehensive research on high-speed TD-ADC design and proposed a single-channel voltage-scalable 8 GS/s 8-bit TD-ADC in 28 nm CMOS. The proposed TD-ADC breaks the speed limit of the traditional TD-ADC by leveraging asynchronous pipeline successive approximation (APSA), which reduces the quantization period to approximate one-stage comparator decision time. A co-design methodology of voltage-to-time converter (VTC) and time-to-digital converter (TDC) has been proposed to optimize the ADC linearity without increasing the complexity or power consumption, reducing the linearity request of VTC. The TD-ADC is fabricated in 28 nm CMOS and occupies an active area of 0.011 mm2, demonstrating 39.2 dB SNDR, 56.1 dB SFDR at 0.9 V 8 GS/s with 85.3 mW power dissipation and 37.6 dB SNDR, 56.3 dB SFDR at 0.7 V 5.05 GS/s with 23.1 mW power dissipation, achieving 143.1 fJ/conv.-step and 74.3 fJ/Conv.-step Nyquist FoMW, respectively. Furthermore, a low-voltage 4 GS/s standalone VTC has also been implemented, which supports the rail-to-rail input with the proposed shrink sampling. The VTC is designed and fabricated in 28 nm CMOS and occupies a 0.0012 mm2 active area. It achieves -56.4 dB THD at 4 GS/s with only a 0.6 V power supply.