Simplified Assembly of Through-Silicon-Via Integrated Ion Traps - Zhao, Peng (2023)
The scalability of surface electrode ion traps has been progressively improved with the on-chip integration of conventionally bulk components. Based on the development of through silicon via (TSV) integrated ion trap, in this work, we further simplify the back-end assembly process by patterning a redistribution layer (RDL) onto customized ceramic pin grid array (CPGA) package. This RDL has internal connection with CPGA pin on the back side, rerouting the electrical signal and facilitating the direct bonding of TSV trap and CPGA. The patterned neighboring RDL has an averaged resistance of 4.5 × 1012 , three orders of magnitude higher than that of TSV trap itself. As compared to the previous assembly (glass interposer wire bonded to a conventional CPGA), a small parasitic capacitance increase of 0.1 pF of the customized CPGA is observed. Radio frequency (RF) electrical tests indicate that the trap on customized CPGA will not induce additional power loss. Meanwhile, due to the high thermal conductivity of ceramic materials, the heat dissipation capability of customized CPGA is boosted. The functionality of TSV trap on customized CPGA is also demonstrated by trapping and laser cooling the 88Sr+ ions. The measured heating rate (21 quanta per millisecond for an axial frequency of 300 kHz) is comparable with the trap assembled in previous approach. This indicates that the CPGA with built-in RDL is fully compatible with ion trapping applications, providing a new approach towards compact, flexible, and robust ion trap assembly.