High-speed and energy-efficient asynchronous carry look-ahead adder

• Main Authors: Balasubramanian, Padmanabhan, Liu, Weichen
• 其他作者: School of Computer Science and Engineering
• 格式: Article
• 語言: English
• 出版: 2023
• 主題: Engineering::Computer science and engineering::Hardware; Engineering::Electrical and electronic engineering::Integrated circuits; Asynchronous Circuits; Arithmetic Circuits; Digital Logic Design; Digital Circuits; Low Power Design
• 在線閱讀: https://hdl.handle.net/10356/170903
• 機構: Nanyang Technological University

Addition is a fundamental computer arithmetic operation that is widely performed in microprocessors, digital signal processors, and application-specific processors. The design of a high-speed and energy-efficient adder is thus useful and important for practical applications. In this context, this paper presents the designs of novel asynchronous carry look-ahead adders (CLAs) viz. a standard CLA (SCLA) and a block CLA (BCLA). The proposed CLAs are monotonic, dual-rail encoded, and are realized according to return-to-zero handshake (RZH) and return-to-one handshake (ROH) protocols using a 28-nm CMOS process technology. The proposed BCLA has a slight edge over the proposed SCLA, and the proposed BCLA reports the following optimizations in design metrics such as cycle time (delay), area, and power compared to a recently presented state-of-the-art asynchronous CLA for a 32-bit addition: (i) 32.6% reduction in cycle time, 29% reduction in area, 4.3% reduction in power, and 35.5% reduction in energy for RZH, and (ii) 31.4% reduction in cycle time, 28.9% reduction in area, 4.4% reduction in power, and 34.4% reduction in energy for ROH. Also, the proposed BCLA reports reductions in cycle time and power/energy compared to many other asynchronous adders.