Investigation of a modified NPN transistor in CMOS structures for enhanced ESD-induced latch-up protection - Mo, Zhiyuan (Nanyang Technological University, 2023)
Integrated circuits (ICs) are vital in modern electronics, including everyday life, industrial manufacturing and military equipment. Reducing transistor size and improving performance requires shrinking the gate oxide layer, which makes ICs more fragile and vulnerable to electrostatic discharge (ESD). ESD can occur at every stage of IC production, making ESD protection critical to improving IC reliability. This paper presents a systematic approach to ESD protection for full chip network design and a design window for effective ESD operation. Four basic requirements for ESD protection devices are discussed, namely robustness, sensitivity, effectiveness and transparency. Various device architectures are described, including diodes, bipolar junction transistors (BJTs), grounded gate NMOS and silicon-controlled rectifiers, and their compatibility with chip fabrication processes. Three ESD discharge models, namely the machine model, the human model and the charged device model, are commonly used to test ESD protection performance, while transmission line pulse (TLP) testing is widely used to assess the effectiveness of ESD protected devices. This Dissertation also elucidates the mechanisms behind avalanche and thermal breakdown and how they relate to the important ESD protection parameters of trigger point voltage, sustaining voltage and failure current. Although this Dissertation focuses on High Voltage NPN (HVNPN) devices, the models and explanations presented are useful for the design of all ESD protection devices. In summary, this Dissertation provides a comprehensive understanding of ESD protection mechanisms and the importance of taking robustness into account when designing ESD protection devices.