Design and simulation of CMOS-based ternary logic arithmetic circuits using TSMC 40nm technology - Vivekanantham, Rithikha (Nanyang Technological University, 2024)
In recent years, there has been growing interest in multi-valued logic (MVL) circuits, especially ternary logic circuits, due to their higher information density compared to binary logic systems. However, challenges persist regarding the fundamental construction of MVL circuit standard cells and the issues of CMOS fabrication compatibility. In this project, various ternary arithmetic circuits including balanced and unbalanced half as well as full adders are designed.