A reconfigurable in-memory-computation architecture with in-situ update and shift capability - Liu, Yihe (2024)
This work proposes a storage element (SE) design for in-memory computing (IMC). Using the proposed SE design, an IMC array has been constructed to enable in-situ updates of stored weights. Compared with some existing related works which employ 2n bit cells for storing an n-bit value, the proposed structure in this work exhibits a O(n) complexity of area overhead, which means that only n bit cells are needed to store n-bit values, offering a significant improvement in silicon area usage. Compared to the purely digitally-controlled weight update schemes, the approach proposed in this work demonstrates an approximate 1.47× increase in power consumption. Furthermore, it exhibits superior robustness compared to existing work. Additionally, the proposed SE design can achieve the necessary shift functionality in the cutting-edge floating-point (FP)-IMC architecture through simple control mechanisms.