Low power digital multiplier IC design - Luo, Weiran (Nanyang Technological University, 2025)
Multipliers constitute a crucial component of integrated circuits and are extensively employed in the realm of digital signal processing. The performance of multipliers frequently dictates the overall performance of circuits and devices. Reducing the power consumption of multipliers represents a significant aspect of optimizing their design. This dissertation initially introduces the principles of multipliers and delves into several prevalent multiplier structures and algorithmic principles, such as the carry-save adder, 3:2 compressor, and Booth algorithm. Subsequently, an optimized low-power structure is proposed, accompanied by its simulation and synthesis results. The comprehensive findings are presented in a format of reports.