Bai, J., & Xiaohong, T. (2025). Analog circuit layout design based on cadence virtuoso and calibre. Nanyang Technological University.
استشهاد بنمط شيكاغوBai, Jiaming, و Tang Xiaohong. Analog Circuit Layout Design Based On Cadence Virtuoso and Calibre. Nanyang Technological University, 2025.
MLA استشهادBai, Jiaming, و Tang Xiaohong. Analog Circuit Layout Design Based On Cadence Virtuoso and Calibre. Nanyang Technological University, 2025.
تحذير: قد لا تكون هذه الاستشهادات دائما دقيقة بنسبة 100%.