Capacitance extraction of interconnects via machine learning - Zhang, Yiming (Nanyang Technological University, 2025)
As Very Large-Scale Integration (VLSI) technology advances and the complexity of integrated circuits (ICs) increases, the precise extraction of interconnect capacitance is becoming increasingly crucial. Current physics-based methods, although accurate, are grounded in Poisson's equations and often slow in the iterative IC design explorations where they are executed repetitively. To address this gap, this research employs machine learning models as faster alternatives for extracting 2D capacitance of interconnects and chips. Compared with Decision Trees and Backpropagation (BP) Neural Networks, the Gradient Boosted - Deep Neural Network Regression (GB- DNNR) model achieves the lowest average error rates, demonstrating higher accuracy on both training and testing datasets. Notably, the proposed method significantly reduces capacitance extraction time when compared with traditional physics-based methods. Numerical results demonstrate that the machine learning-based approach can considerably enhance the efficiency of the capacitance extraction for IC design process. This advancement has broader implications for the field of electronic design automation, as machine learning could play a critical role in the future development of more efficient and faster IC designs.