Five-stage pipelined RISC-V SoC design - Yang, Yulong (Nanyang Technological University, 2025)
With the rapid development of the Internet of Things (IoT), embedded systems and artificial intelligence, there is an increasing demand for low-power and high-performance processors. RISC-V, as an open-source, streamlined and scalable instruction set architecture, is gradually becoming an ideal choice for these fields due to its flexibility and low-cost advantages. Firstly, this dissertation designs and implements a five-stage pipeline-based RISC-V core based on RV32IM instruction subset, which consists of 44 basic integer instructions (all of the instruction set of the RV32I except fence, ecall, and ebreak) and an extended 8 integer multiply-divide instruction (RV32M) for a total of 52 executable instruction sets. The design functions as an arithmetic (add, subtract, multiply and divide) and logic instruction, a branch and jump instruction, and a load and store instruction. In addition, to verify functional integrity, the dissertation designs two RAMs (4 KB), integrated with the RISC-V core, to build a simple SoC (System on Chip). Tests were performed using the official instruction set test files. This design is compiled with Verilog HDL, verified by VCS software, and synthesized by DC software. The synthesized results show that the RISC-V SoC uses 211,158 transistors; Total power dissipation is 16.29 mW, and the timing slack is 0.29 when operating at 167 MHz. Maximum operating frequency up to approx. 180 MHz. As evident from simulation result, the RISC-V SoC has met the anticipated objectives and aligns with the specifications.