Five-stage pipelined RISC-V SoC design

• 主要作者: Yang, Yulong
• 其他作者: Gwee Bah Hwee
• 格式: Thesis-Master by Coursework
• 語言: English
• 出版: Nanyang Technological University 2025
• 主題: Engineering; Digital IC; RISC-V
• 在線閱讀: https://hdl.handle.net/10356/183432

With the rapid development of the Internet of Things (IoT), embedded systems and artificial intelligence, there is an increasing demand for low-power and high-performance processors. RISC-V, as an open-source, streamlined and scalable instruction set architecture, is gradually becoming an ideal choi...