FPGA implementation of a speech coder - Tay, Zar Myint. (2010)
In this project, one of the speech compression methods, a LPC 10 decoder was designed by using VHDL. In the designed LPC decoder, two different types of speech production model were designed and used to compare their performances. The first model used two adders, two multipliers and one substractor and the second one used four multipliers, four adders and one substractor. It was found that the first model took three cycles more than the second one to complete the one sample. On the other hand, the first model only used total 19778 gates while the second one used 28901 gates. Therefore the second model took more resources.