High performance architecture for move generation in computer chess : an FPGA based implementation - De Silva, C. R. (2008)
This thesis describes the design of a high performance parallel move generator architecture suitable for a high-speed chess computer. It illustrates how the complicated single task of chess move generation can be decomposed into several simple and independent atomic processors. These processors are then implemented in hardware, enabling them to operate in parallel contributing to the overall system throughput. Two novel concepts that contribute mostly to high performance architecture are introduced in this thesis.