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  _____      ___    __    __   _    _    _    _   
 /  ___||   / _ \\  \ \\ / // | || | || | \  / || 
| // __    | / \ ||  \ \/ //  | || | || |  \/  || 
| \\_\ ||  | \_/ ||   \  //   | \\_/ || | .  . || 
 \____//    \___//     \//     \____//  |_|\/|_|| 
  `---`     `---`       `       `---`   `-`  `-`

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Text this: Digital system design with FPGA using verilog HDL