Design of ultra-low power asynchronous-logic quasi-delay-insensitive circuit templates - Chng, Clive Kuan Nee. (2011)
This report presents the design of Ultra-low power asynchronous Quasi-Delay-Insensitive (QDI) library cells and circuits templates using the CMOS 65nm Bulk process technology. Asynchronous systems are self-timed circuits that employ hand-shaking protocols instead of relying on a global clock to communicate like in all synchronous systems. In particular, Quasi-Delay-Insensitive library cells are circuits that do not assume any time delay except for a set of designated wire forks or fan-outs labeled as isochronic to function properly, thus making these circuits more robust to different varying conditions. These basic library cells can be employed by IC designers to design larger, more complex circuitry for various functionalities according to market demands. The report also presents the process flow of an IC design and the use of Electronic Design Automation (EDA) tools such as Cadence Virtuoso® Schematic Capture and Cadence Virtuoso® Layout Editing to design and simulate schematic diagrams and cell layouts of the library cells respectively. During the designing stage, crucial checks known as Design Rule Check (DRC) and Layout Versus Schematic (LVS) are performed to ensure that the cell designs adhere to proper design rules and functionality. For application purposes, parasitic capacitances of the cells are also extracted to mimic realistic circuit parameters. Towards the end of the report, the simulation results between pre-layout and post-layout are observed and compared. Finally, Synopsys Nanosim is used to test the library cells which have been programmed based on the PCHB approach, to realize a 64-bit Kogge-Stone tree adder design.