Enhanced low-power high-speed probabilistic adders for error-toerant application - Zhu, Ning (2011)
In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. To overcome all the possible errors is a very expensive task. It not only consumes a lot of power but also degrades the speed performance. With the concept of “error-tolerant” (ET), which allows the existence of certain amount of errors, improvements in power consumption and/or other performance metrics can be achieved. In this design, the concept of error-tolerant has been extended to the field of circuit design. When “imperfect” algorithms and circuit structures are employed, a substantial yield for an error-tolerant digital circuit, in terms of power consumption, speed performance, and transistor count, can be realized. An adder is the basic digital circuit component, which is widely used in many areas. Adopting the ideas and techniques in Error-Tolerant technology in the design of digital adders, a innovative type of adder—Probabilistic Adder for Error-Tolerant Application (ETA) has been designed. In conventional design, obtaining high speed usually means more power will be consumed and low power will normally degrade the speed of a circuit. To breakthrough this bottleneck in conventional technologies for designing a truly low-power and high-speed digital circuit, a new metric besides power and speed should be brought into the design process. In the proposed designs, accuracy plays the role of such a new metric. By sacrificing some degree of accuracy, great improvements in both power consumption and speed performance can be achieved. Several different implementations of the enhanced ETA have been proposed in the report, namely the ETA Type II (ETAII), ETA Type III (ETAIII) and ETA Type IV (ETAIV). The ETAII is based on the idea that in most cases the carry signal for a bit position is determined by several neighboring bits instead of all the bits on its right. Hence, the critical path of the whole circuit can be greatly curtailed by dividing the whole adder into a number of blocks and conducting the addition operations in each block concurrently.