Low, H. G., & Koh, L. M. (2008). Electrical design, modelling and optimization of a low-cost wafer level chip scale package (WL-CSP).
استشهاد بنمط شيكاغوLow, Hong Guan., و Liang Mong Koh. Electrical Design, Modelling and Optimization of a Low-cost Wafer Level Chip Scale Package (WL-CSP). 2008.
MLA استشهادLow, Hong Guan., و Liang Mong Koh. Electrical Design, Modelling and Optimization of a Low-cost Wafer Level Chip Scale Package (WL-CSP). 2008.
تحذير: قد لا تكون هذه الاستشهادات دائما دقيقة بنسبة 100%.