Electrical design, modelling and optimization of a low-cost wafer level chip scale package (WL-CSP) - Low, Hong Guan. (2008)
This report presented the design of a Wafer Level Chip-Scale Package (WL-CSP) using a patented UTAC’s Build Up (UBU) technology, which is a low-cost packaging process with a redistribution layer. From various papers, it had been shown that WL-CSP has superior electrical performance over conventional and advanced packages.