Study of leakage and degradation in metal nanocrystal-embedded gate stacks - Lwin, Zin Zar (2013)
Nanocrystal (NC) memories have attracted a lot of research attentions as a promising candidate to reduce defect-related charge loss and to overcome scaling limitation in conventional floating gate memories. Most work on metal nanocrystal (MNC) has focused primarily on the materials and fabrication issues, while the reliability aspects have been greatly ignored, such as inter-dot tunneling among NCs, the charge loss mechanisms and their performances in the degraded dielectric gate stacks which are of utmost importance for the device optimization and future scaling. This work focuses on the degradation and reliability of MNC embedded gate stacks, contributes to a deeper understanding of MNC performances in the degraded dielectric gate stacks and its charge transport behaviors, and reports extensively on the reliability characterization of both single-layer and dual-layer MNC embedded gate stacks. To enable strong gate coupling and low operating voltage, NCs are conventionally embedded in the high-κ layer. Therefore, the overall dielectric gate stack in conventional NC memories typically consists of a tunneling oxide layer and a NC-embedded high-κ layer. It is thus important to understand the performance of MNCs in the case of the individual dielectric layer degradation. Firstly, we report the influence of dielectric degradation on charging and discharging characteristics of MNCs embedded in high-/SiO2 gate stacks. It is found that the charging and discharging phenomena of the MNCs and leakage mechanism in the degraded gate stacks are strongly dependent on the lateral charge tunneling/hopping among the NCs. Our experimental results show that the localized breakdown not only affects charge holding capability of the affected NCs, but also provides a leakage path for the charges stored in the surrounding NCs. It indicates the existence of lateral charge diffusion in the MNCs. Next, the post-breakdown characteristics of the conduction path formed in the individual different dielectric layer (either SiO2 or NC-embedded Al2O3) are identified. The first layer to breakdown is determined based on the physics underlying the Coulomb charging energy in relation to thermal energy gained by electrons at low voltage and in the very low temperature regime ranging from 11K to 70K. With this approach, the average trap (defect) size in NC-embedded high-κ and SiO2 is further analyzed. It is noted that breakdown in SiO2 leads to lateral charging/discharging among NCs while in Al2O3, it leads to spontaneous breakdown of bi-layer gate stacks owing to high localized trap generation rate around the high-κ dielectric grain boundary and local electric field enhancement in the vicinity of MNCs. To further confirm the lateral charge diffusion of MNCs observed in the degraded dielectric gate stacks, the localized charge transport and lateral charge diffusion phenomena in MNCs are investigated by Kelvin Force Microscopy (KFM) characterization. The results reveal that vertical charge loss and lateral charge diffusion are two competing mechanisms and they can be identified by discharging current measurements at elevated temperatures and KFM characterization. It is found that the MNC with higher work function has a lower inter-dot charge tunneling probability, which is favorable for improved retention in memory applications. However, the vertical charge loss during the initial decay period is a trade-off and hence it could be minimized by using dual-layer (DL) MNC structure wherein electron de-trapped from one-NC layer could be “re-trapped” in the adjacent NC layer. Therefore, the DL-MNC devices with high work function MNCs are chosen to study their intrinsic charge loss mechanisms and inter-dot tunneling and inter-layer tunneling characteristics. A comparative study is performed on the DL devices with inter-layer dielectric (ILD) thickness variation. The temperature and gate-bias accelerated retention measurements and KFM approaches are used. It is found that charge loss in DL structures is mainly due to the internal electric field induced by trapped electrons which depends on the ILD thickness and MNC spacing. When the ILD thickness is comparable to MNCs spacing, the charge distribution in two-MNC layers are similar and the internal electric field induced by charges stored in the MNCs is higher. It leads to the fact that internal-electric-field assisted tunneling dominates at lower temperature. In contrast, when the ILD thickness is larger than the average MNC spacing, less charges are injected in the neighboring MNC layer, resulting in a reduction of both internal electric field and oxide trap alignment possibility with the traps inside the MNCs. Moreover, a thick ILD reduces the electron tunneling probability from one MNC-layer to another during retention. Our findings suggest that an optimized DL-MNCs embedded memory cell could be achieved by defining the ILD thickness larger than the average MNC-spacing for enhancement of retention ability in MNC embedded gate stacks. It implies the possibility of reducing MNC spacing in scaled memory devices by using DL-MNCs with controlled ILD thickness to achieve both increased memory window and prolonged retention. In summary, the dielectric degradation and fundamental reliability issues in MNC embedded gate stacks are investigated in details and comprehensive understanding of inter-dot tunneling and charge loss mechanisms in MNC embedded gate stack is achieved for optimum memory cell design with retention reliability perspective.