Logic-compatible embedded dynamic random access memory design - Wang, Yue (2014)
Nowadays, EDRAMs become a new direction in the research society since it has higher density. However, poor data retention time due to small storage capacitor and various leakage paths has become the main issue, which results in high power consumption and poor read performance. In this FYP, the author develops two circuit techniques to improve the data retention time by analyzing the leakage currents of different EDRAM cell configurations.