Ultra-wideband switches using defected ground structure low pass filter in 65nm CMOS technology - Anak Agung Alit Apriyana (2015)
Designing ultra-wideband switches that can operate from DC to millimeter-wave frequency range is very challenging, and that is especially true when the packaging of the switches is also taken into consideration. Due to nearby cut-off frequency ifc) and maximum oscillation frequency (fmax) of 65 nm CMOS process, the insertion loss at millimeter-wave frequency range is limited because the knee frequency can occur as early as 80 - 90 GHz after which the frequency roll-off is inevitable. At millimeter-wave frequencies range, the parasitic capacitances of the control transistor greatly affect the switch performances, especially the insertion loss, return loss and isolation. Hence, accurate prediction of the parasitic capacitances of the control transistor and their effective compensation technique are proven to be key success to design the ultra-wideband switches. Unfortunately, the process design kit (PDK) models that are provided by the foundry are found to have limited accuracy at high frequency to predict those parasitic capacitances. Due to limitation of the PDK kit in prediction of extrinsic parasitic capacitances of the control transistors, unit cell modeling approach is proposed to model the parasitic capacitances of multi-fmgers transistor and to enhance the original PDK modeling. The modeling is based on simulation approach, which is done using full wave electromagnetic (EM) simulation of the devices using High Frequency Structure Simulator (HFSS). Firstly, the parasitic capacitances of the unit cells are extracted from the Y-parameters. Then, parasitic capacitances of the multi-fingers transistor are obtained from linear scaling of its unit cell. The error is maintained to be less than 5%. The main benefit of unit cell modeling is its scalability and flexiblity since any complicated transistor layout or structure can be built up by the unit cells and their parameter can be represented by scaling ofunit cell parameter. In addition to transistor modeling, modeling of electrical interconnect, coupling between lines, ground current distribution are also crucial. The modeling of these effect are also done with full EM analsis using HFSS. This EM analysis is necessary to provide a much deeper physical insight into the switch behavior and to predict the otherwise unforeseeable parasitic senes resonance at high frequency. Hence, EM simulation is done after every schematic simulation and post layout simulation. A novel technique to simulate an on-state switching transistor is proposed and highlighted. The circuit modeling is made by including all extracted extrinsic parasitic inductances, capacitances, and resistances, especially the drain-to-source parasitic capacitances that are introduced by the overlapped multi-fingers metallization ofthe transistors. Finally, the electromagnetic analysis and circuit modeling are validated with the measurements of the SPST switch over the frequency ranges from 1 to 110 GHz and 140 to 170 GHz, respectively. Performance, chip size, cost, fabrication simplicity, and design flexibility are the typical design trade-offs of ultra-wideband switch design. Most of the previous solutions that have been proposed by some researchers are still not the optimum solutions to gain the best compromise of the design trade-offs. The main obstacles are to find an efficient way to compensate the parasitic capacitances of the control transistors across ultra-wideband operating frequency. In summary, transmission lines (TLs) or inductors are used as the compensating elements. The use of TLs as the compensation method has the benefit of wideband characteristic due to inherent wideband properties of TLs. However, their huge sizes are their main issues. The compensation method with inductor can save some silicon area but the compensation can only cover narrow band frequency range. In this research, a novel concept of applying a defected ground structure (DGS) to design switches is introduced for the first time. The DGS structure has such advantages as consuming less silicon area and providing another degree of freedom in the design of switches. To prove the concept, firstly, a single-pole single-throw (SPST) switch using a DGS low pass filter (DGS LPF) in a 65 nm CMOS technology is analyzed, designed, and characterized. It is showed that the DGS LPF SPST switch of size 300Jlm x 247 urn can cover an ultrawideband from DC to 77 GHz. Secondly, a novel concept to design single-pole multi-throw (SPMT) switches, which are consisting of single-pole double-throws (SPDT), single-pole four-throw (SP4T) and single-pole eight-throw (SP8T) switches, using DGS LPF are presented. The switches are designed in 65 run CMOS Technology. The overall footprint of SPDT and SP4T are less than 285 x 88 Ilm2 and 285 x 299 Ilm2 respectively and can cover ultrawideband from DC to 75 GHz. The total areas and active areas of the SP8T switches are less than 860 x 460 Ilm2 and 425 x 165 Ilm2 respectively and designed to operate from DC - 15 GHz. DOS LPF can also be used to improve the switch linearity by floating the bulk of control transistor. The switch is done in standard CMOS process. Due to its wideband characteristic, linearity can be improved for wider frequency range than the LC-tuned approach. Due to its enhanced inductance and additional degree of freedom, we have more flexibility to balance overall switch performances. The effect of packaging to switch performances is also studied. The study aims to find the most suitable packaging for the switches. Among the various types of packaging, flip chip packaging is considered being a strong candidate due to its low loss, small form factor, moderate cost, excellent reliability, and . most of its manufacturing issues and problems have been kno-wn. The influence of two types of flip chip packaging, which are chip scale packaging (CSP) with LTCe process and wafer level packaging (WLP), to frequency responses of SPST, SPDT and SP4T switch are investigated. Between CSP and WLP, WLP solution is found to be the suitable candidate in the packaging of ultra-wide band switch. With its smaller bump size, shorter bump pitches and finer lithography process, a long distribution lines as in chip scale packaging is avoided. Its small form factor produces lesser parasitic effect that only affects the frequency response of the switch at much higher frequency. As a result, the chip broadband performances still can be maintained after the introduction of the packaging.