Data converters using continuous time sigma delta modulators with VCO-based integrator and quantizer for ultra low power applications - Neelakantan Narasimman (2017)
Ultra-low power operation is highly desirable for circuits and systems, which run on strict power budgets. The demand has increased with the rise in applications, which work on harvested energy such as autonomous sensor nodes. Data converters are an inevitable part of sensor interface systems and high-performance communication circuits used in various biomedical and portable computing applications. Among different variants of data converters available, the ones using continuous time ΣΔ modulators are extremely popular for achieving high resolution with excellent energy efficiency. Nevertheless, with technology/supply voltage scaling, prominence of second order effects and the absence of voltage headroom have made the design of traditional ΣΔ modulators challenging. VCO-based ADC is a promising solution to address this problem. Since CMOS inverter based ring oscillator is used as VCO, analog information is contained in the phase/frequency of the oscillations. Thus, quantization is performed in the time domain as opposed to voltage domain in the conventional quantizer. Since continuous scaling of the CMOS technology aids the digital nature of the circuit components, VCO-based ADCs form excellent candidates for ultra-low voltage operation and could be used as either quantizer or integrator in a continuous time ΣΔ modulator. However, VCO-based ADCs have various challenges for achieving ultra-low power targets, such as small voltage margin, noise, and nonlinearity. This thesis focuses on the design and development of data converters using continuous-time ΣΔ modulators with VCO-based integrator/quantizer for ultra-low power applications. Firstly, existing architectures and designs for VCO-based ADCs and other ultra-low voltage ΣΔ modulators are carefully analyzed. Solutions xvi proposed in the thesis are broadly divided into three parts that include design, analysis and measurement results of three test chips. I- Open loop First order ΣΔ modulator using VCO-Frequency Delta Sigma Modulators (FDSM) VCO-based ADC, when employed in the open-loop configuration, gives first order noise shaping for the quantization noise. However, the non-linear voltage to frequency tuning characteristics of a VCO adds distortions at the output. While pseudo-differential operation could correct the even order distortions, odd order harmonics are difficult to remove. This chapter presents a calibration scheme to correct odd order harmonics for realizing a linear open loop VCO-based ADC. The proposed calibration scheme uses digital background calibration architecture operating at ultra-low supply voltages. A replica VCO is used to calibrate the nonlinearity, and a lookup table, in the signal path, is filled with corrected values. The proposed calibration method is at least 256 times faster than other state-of-the-art ones. A prototype design was fabricated in commercial 65nm CMOS technology. Measurement results show that the proposed calibration technique improves the SNDR of the open loop VCO-based ADC from 42dB to 55dB over 10 KHz signal bandwidth while consuming 1.15 μW power. II - Closed loop first order ΣΔ modulator using VCO as an Integrator The performance of an open loop VCO-FDSM is limited by the amount of Nonlinearity correction it can achieve. The mismatch between replica VCO and main VCO, circuit non-idealities at low voltage supplies limit the same. In this chapter, alternate architecture for better linearity is discussed. The phase of a VCO is xvii proportional to the integral of its input. Thus, VCO can act as a linear integrator if the input to the VCO is within its linear range. Measuring the phase output of the VCOs gives integral of the input. Multi-bit output, when fed back, maintains the VCO input within its linear range. However, one of the main challenges is the variation of the circuit characteristics at ultra low voltages. This work proposes an ultra-low voltage, VCO-based sigma delta modulator with self-compensated current reference against process and temperature variations. The proposed current reference generator sets the feedback current of the multi-bit Non-Return-to-Zero (NRZ) DAC and the VCO tuning coefficient (KVCO) at ultra-low voltage. A test chip fabricated in 65nm CMOS technology demonstrated successful operation at 0.3 V. It consumes 510nW and occupies 0.015mm2. The proposed VCO-based ΣΔ modulator achieves peak SNDR of 56.1dB at 0.3 V and 10 kHz input bandwidth, and FoM of 49fJ/conv.-step. Detailed analysis of the architecture needed for design consideration will be provided. III - Capacitance to Digital Converter using Continuous Time Second Order ΣΔ modulator with VCO as integrator/Quantizer This work is an extension of dual-VCO based integrators towards a specific application. Early detection/monitoring of diastolic dysfunctions in the human heart can be done using a non-invasive, highly sensitive, portable sound recording system with cardiac sound wave characterization. Capacitive MEMS microphones, which are based on the modulation of electrical capacitance by the acoustic pressure wave from the heart sound, are an excellent choice for the recording device. Since capacitive sensors do not consume static power, they are very suitable for such portable low-power and energy-constrained applications. However, the energy xviii consumption will be dominated by that of the interface circuit that converts capacitance value to a digital output. This chapter proposes a novel architecture and circuit implementation for capacitance to digital conversion. Proposed capacitance-to-digital converter (CDC) uses a continuous time second-order delta-sigma modulator with multi-bit quantization for digitizing. Along with active-RC integrators using OTAs, this CDC employs VCO-based integrator with multi-bit quantization to achieve second order noise shaping. The proposed CDC has been realized in a 0.18um CMOS technology. Measurement results show that the CDC achieves 13-bit resolution for capacitance-to-digital conversion with a measurement time of 0.125ms while consuming only 42uA from 1.2V supply. The design achieves a state-of-the-art figure-of-merit of 0.79pJ/conversion-step.