Simulation study of lots with time window constraints in the semiconductor wafer fabrication facility - Prasetya, Samuel Juan (2017)
In response to an increasingly fierce competition faced by semiconductor manufacturing companies, improvements in operational practices are deemed to be the primary drivers to achieve the necessary cost reductions and profit maximization. This is true because it enables the factories to increase their productivity through better decision-makings. One of the most prominent issues encountered in the fab is caused by the presence of lots with time window constraints. Numerous redundant works are required when these constraints are violated. It occurs as most tools do not have an appropriate algorithm to select the right lot from the buffer in such a way that all constraints are satisfied. This project therefore seeks to alleviate this problem by means of simulation method. Case studies that can partially represent the situations in the wafer fab are provided. The simulation models are then developed to replicate these case studies. Subsequently, the performance of the models is monitored under different parameters and circumstances. The main goal is to attain the ratio of maximum to average cycle time of a studied lot, depending of the fab settings that it is exposed to. To enable a faster simulation run time, alternative ways are also introduced. Moreover, the methodologies, important relationship, and insightful discoveries that can be used to optimize the semiconductor manufacturing process are further elaborated in this report. All experiments are basically performed to establish quick and reliable control strategy that can help to determine whether the studied lot can be released for further processing without breaching its respective time window constraints.