Printed electronics : modeling, variations and bending - Zhou, Jia (2018)
The sanguine projection of the gargantuan growth of Printed Electronics to a large extent assumes that intelligent (embodying analog, mixed-signal and digital signal processing functionalities) Printed Electronics circuits/systems can be realized. This also largely assumes that the printing can be realized on flexible low-cost substrates by green, low-cost, on-demand and scalable printing and that all chains in the entire supply chain is manageable/established. However, at this juncture, Printed Electronics-only circuits/systems remain nascent, i.e., Printed Electronics-only circuits are often rudimentary - lacking sophisticated signal processing functionalities. This is particularly the case for Fully-Additive Printed Electronics. The overall objective of this research project is to augment intelligence in Printed Electronics. Specifically , this research focuses on the second chain (printing) and the third chain (circuits) of the supply chain of the emerging Printed Electronics technology from following imperative perspectives: manufacturability (e.g., low process variations), functionality (e.g., full-fledged electronics, and bendability of the substrates), designability (e.g., availability of the Process Development Kit), and low cost (e.g., Fully-Additive, All-Air, Low-Temperature process). A number of contributions are made herein with respect to these imperatives. First, for the manufacturability of Printed Electronics, a novel screen printing Low-Cost Fully-Additive all-air-processed low-temperature Printed Electronics printing process featuring very-low process variations is proposed. Specifically , the process variations are ±4.9% p (carrier mobility) and ±0.43V ~h (threshold voltage) . To the best of our knowledge , this is the smallest p variations amongst all reported Fully-Additive printing processes, and comparable to the best of Subtractive processes. These very low variations are achieved by blade coating the semiconductor layer comprising a polymer-small molecular blend in a dual-solvent system , yielding precise control of the semiconductor film formation. Further by means of careful layout , the matching between our two printed transistors is markedly improved from 7.2% (arising from ±4.9% p and ±0.43V Vth variations) to 2.1%- to date , the best reported matching. Second, for the functionality of Printed Electronics, a comprehensive investigation into the effects of concave/convex bending to printed circuit-elements and basiccircuits is presented, and a novel localized self-compensation means is proposed. The variations of said circuit-elements range from mild-to-severe, depicting that for accurate transfer-functions, capacitor-based circuits are preferred; and the variation direction of capacitors and resistors is the same, but the converse of transistors. For the inverter and ring oscillator, the variations range from moderate to very-severe and severe to extremely-severe respectively for diode-connected and zero-VGS connected topologies. This depicts that diode-connected circuits are preferred; and for speed, concave-bending is preferred. For the op-amp, the gain and gain-bandwidth variations range from mild-to-severe; and concave- and convex-bending is respectively preferred for gain-bandwidth and gain. By leveraging on the process-simplicity of our Fully-Additive all-air-processed low-temperature printing-processes, we propose a novel localized self-compensation means involving the partition of a given circuit-element/ circuit into two-halves, each placed on the top/bottom of the flexible substrate surface. The proposed means is highly efficacious - the reduction of variations ranges from ~2x to >100x, yet without power, hardware or substrate-area overheads but with additional printing steps. Third, for the designability of Printed Electronics, an 'Open-Platform' PDK for our Fully-Additive all-air-processed low-temperature printing process with very low process variations is developed. Our PDK embodies a novel simple yet accurate transistor model that can not only accurately model the printed transistors depending on their layout and when they are flat (unbent substrate) but also accurately model the process variations when they are bent (bent substrate). This PDK accommodating bending 1s important for Printed Electronics circuits/systems whose substrate is adhered to uneven surfaces or bent to fit odd spaces, thereby expanding the applicability of Printed Electronics circuits/systems. The efficacy of the proposed Open-Platform and the proposed Printed Electronics transistor model is verified by means of comparisons between simulations of and measurements on basic individual printed electronic elements and for several fundamental printed digital and analog circuits. These comparisons include when the substrate is flat and bent, depicting that bending is not necessarily detrimental, but may be advantageously exploited. The proposed PDK is compatible with commercial computer aided design simulation tools.