Scan implementation and toggle coverage estimation for voice subsystem - Mohan, Vivek (2019)
With shrinking technology node, the reliability and testability of integrated circuits has become crucial. Larger designs pose greater challenges to various aspects of Chip design including Design for Testability (DFT). DFT techniques are implemented to provide controllability and observability of the internal nodes of circuits by insertion of additional test logic into the design. This dissertation studies the implementation of full-scan design for the voice sub-system in the DFT flow. Scan Insertion is the first step in the DFT Scan flow, followed by pattern generation using ATPG to detect targeted faults. The EDA tool generated test pattern in the Scan process is essentially a stimuli written out as a test bench which is then simulated and verified. Stress testing involving intense temperature, pressure, workload, memory usage, clock speed, voltages etc., is performed to test the reliability, stability and longevity of the integrated circuit. Dynamic stress testing involves toggling of circuit nodes. Thus, Stress test performed at the time of burn-in involves toggle fault model. Toggle fault coverage provides a quick way to determine the extent of control over circuit nodes by driving them to logical 0 or 1 voltage, with less overhead compared to stuck-at model. This dissertation also presents the experiments performed and the results obtained for estimating the toggle coverage of the design under test using pseudorandom patterns generated from a 32-bit linear feedback shift register (LFSR) done as part of the DFT flow. The LFSR generated pseudorandom patterns were converted to ATPG readable pattern to perform toggle fault simulation and coverage estimation. This approach of generating patterns with non-complex LFSR circuitry seems to be a feasible option for test analysis using the toggle fault model for future DFT integrations with enhanced LFSR pattern generation to obtain higher toggle coverage.